1. Field of the Invention
The present invention relates to a GaN-based semiconductor device such as a GaN-based hetero-junction field effect transistor (HFET) or the like and a method of manufacturing the GaN-based semiconductor device.
2. Description of the Related Art
Patent Reference 1 has disclosed a conventional GaAs-FET. FIG. 10 shows the GaAs-FET disclosed in Patent Reference 1. The GaAs-FET has a source electrode (a first conductor) 2, a drain electrode 4, and a gate electrode 3 on a surface of a GaAs semiconductor substrate 1, and a bottom electrode (a second conductor) 7 on a bottom surface of the semiconductor substrate 1. The GaAs-FET is provided with a via hole 8 connecting the source electrode 2 and the bottom electrode 7 in the semiconductor substrate 1. The via hole 8 is filled with a third conductor. The GaAs-FET has an insulating film 6 formed between the third conductor in the via hole 8 and the semiconductor substrate 1.
Generally, in the FET of a planar type, three bonding pads are required for three electrodes, thereby increasing a size of an element. Therefore, in the GaAs-FET shown in FIG. 10, the via hole 8 is formed from a bottom surface of the substrate 1, so that the bottom electrode 7 and the source electrode 2 are electrically connected, thereby reducing one of the three bonding pads. Further, in order to prevent a breakdown voltage from lowering, a portion of the via hole 8 is covered with the insulating film 6.
As opposed to the GaAs-based material, the GaN-based semiconductor material has a larger bandgap energy and high heat resistance capable of operating at a high temperature. Accordingly, a field effect transistor or the like using the GaN-based material has been developed.
Patent Reference 2 has disclosed a GaN-based HEMT (High Electron Mobility Transistor) formed of a gallium nitride type semiconductor compound as a GaN-based semiconductor device. In the GaN-based HEMT, a buffer layer is formed on a substrate if needed, and a carrier drift layer and a carrier supplying layer epitaxially grown thereon. Further, an electrode is formed thereon.
In the semiconductor device of the planar type, it is possible to obtain a large electric power with a small area. However, a current density flowing in a wiring portion tends to be large, and electro-migration (or a disconnection of the wiring portion) tends to occur. In the planar device (or planar power device), an electrode is often formed in a comb shape. Accordingly, the current density may exceed 2×106 A/cm2, there by making it difficult to obtain sufficient resistant to the electro-migration (EM) with an electrode formed of Au or Al. In order to solve the problem, it is necessary to provide a structure for reducing the current density.
To this end, a thickness of an electrode increases for reducing the current density, or a portion of a source electrode is grooved for flowing a current vertically. In order to sufficiently reduce the current density, however, it is necessary to increase the thickness of the electrodes up to 20 μm while the electrode has a width of 10 μm, thereby increasing a height of the electrode. When the electrode has an excessive height, the electrode may be broken upon resin molding. Further, the electrode may be disconnected or a passivation film is cracked due to a thermal stress or the like. When the portion of the source electrode is grooved, it is possible to drastically reduce the current density less than 1 kA/cm2. Patent References 3 and 4 have disclosed technologies for flowing a current vertically.    Patent Reference 1: Japanese patent publication No. H05-021474    Patent Reference 2: Japanese patent publication No. 2006-173582    Patent Reference 3: Japanese patent publication No. 2006-086398    Patent Reference 4: Japanese patent publication No. 2004-363563
In the conventional GaN-based semiconductor device disclosed in Patent Reference 1, an active layer formed of the GaN-based semiconductor is formed on a silicon (Si) substrate to form an epitaxial wafer having a large distortion. In order to restrain warping or crack, it is necessary to increase a thickness of the substrate greater than 500 μm. Accordingly, it is very difficult to form a via hole from a bottom side of the substrate.
Even when the via hole is formed from the bottom side of the substrate, the via hole has a depth greater than 500 μm as opposed to a width of 10 μm. Accordingly, it is difficult to form an insulating film between a conductor in the via hole and the semiconductor substrate deeply enough into the via hole.
In the semiconductor device disclosed in Patent Reference 3, a first source electrode and a second source electrode are formed separately from a via hole metal in ohmic contact with a conductive substrate, thereby making a manufacturing process complicated and costly. In addition, it is difficult to form a via hole metal only in a bottom surface of a trench.
In the semiconductor device disclosed in Patent Reference 4, a source electrode and a via hole metal in ohmic contact with a conductive substrate are formed integrally. The source electrode is formed of a metal in ohmic contact with the conductive substrate and in Schottky contact with a first semiconductor layer and a second semiconductor layer, thereby increasing an on-resistance thereof.
An object of the present invention is to solve the problems in the conventional technologies.